Negative capacitance effect in a ferroelectric-based gate stack provides an effective solution for hysteresis-free steep-slope operation in a MoS2 field-effect transistor.
This is a preview of subscription content, access via your institution
Relevant articles
Open Access articles citing this article.
-
Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
npj 2D Materials and Applications Open Access 07 September 2021
-
Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors
Scientific Reports Open Access 24 June 2019
-
Steep switching devices for low power applications: negative differential capacitance/resistance field effect transistors
Nano Convergence Open Access 28 January 2018
Access options
Access Nature and 54 other Nature Portfolio journals
Get Nature+, our best-value online-access subscription
$29.99 / 30 days
cancel any time
Subscribe to this journal
Receive 12 print issues and online access
$259.00 per year
only $21.58 per issue
Buy this article
- Purchase on Springer Link
- Instant access to full article PDF
Prices may be subject to local taxes which are calculated during checkout
References
Ionescu, A. M. & Riel, H. Nature 479, 329–337 (2011).
Salahuddin, S. & Datta, S. Nano Lett. 8, 405–410 (2008).
Cutaia, D. et al. Symp. VLSI Technology Digest of Technical Papers, 226–227 (IEEE, Honolulu, 2016).
Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Nat. Nanotech. 6, 147–150 (2011).
Si, M. et al. Nat. Nanotech. https://doi.org/10.1038/s41565-017-0010-1 (2017).
McGuire, F. A. et al. Nano Lett. 17, 4801–4806 (2017).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Ionescu, A.M. Negative capacitance gives a positive boost. Nature Nanotech 13, 7–8 (2018). https://doi.org/10.1038/s41565-017-0046-2
Published:
Issue Date:
DOI: https://doi.org/10.1038/s41565-017-0046-2
This article is cited by
-
Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices
Nature Electronics (2023)
-
Investigation of Noise Characteristics in Gate-Source Overlap Tunnel Field-Effect Transistor
Silicon (2022)
-
Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures
npj 2D Materials and Applications (2021)
-
A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon
Nature Electronics (2021)
-
Ferroelectric negative capacitance
Nature Reviews Materials (2019)