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Mechanical integrated circuit materials

Nature volume 608, pages 699–703 (2022)Cite this article

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Abstract

Recent developments in autonomous engineered matter have introduced the ability for intelligent materials to process environmental stimuli and functionally adapt1,2,3,4. To formulate a foundation for such an engineered living material paradigm, researchers have introduced sensing5,6,7,8,9,10,11 and actuating12,13,14,15,16 functionalities in soft matter. Yet, information processing is the key functional element of autonomous engineered matter that has been recently explored through unconventional techniques with limited computing scalability17,18,19,20. Here we uncover a relation between Boolean mathematics and kinematically reconfigurable electrical circuits to realize all combinational logic operations in soft, conductive mechanical materials. We establish an analytical framework that minimizes the canonical functions of combinational logic by the Quine–McCluskey method, and governs the mechanical design of reconfigurable integrated circuit switching networks in soft matter. The resulting mechanical integrated circuit materials perform higher-level arithmetic, number comparison, and decode binary data to visual representations. We exemplify two methods to automate the design on the basis of canonical Boolean functions and individual gate-switching assemblies. We also increase the computational density of the materials by a monolithic layer-by-layer design approach. As the framework established here leverages mathematics and kinematics for system design, the proposed approach of mechanical integrated circuit materials can be realized on any length scale and in a wide variety of physics.

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Fig. 1: Bit abstraction through switching elements and gates.
Fig. 2: Combinational logic design synthesis.
Fig. 3: Two-bit arithmetic operators.
Fig. 4: Demonstration of the sensing, computing and actuating functionalities of a soft mechanical IC material.

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Data availability

All data are available in the main text or the Supplementary Information and are available from the corresponding author upon reasonable request.

Code availability

All code is available in the main text or the Supplementary Information and is available from the corresponding author upon reasonable request.

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Acknowledgements

This research is supported in part by a US Air Force Research Lab (AFRL) Summer Faculty Fellowship, in part by the Air Force Office of Scientific Research, in part by the National Science Foundation (NSF) Faculty Early Career Development Award (number 2054970), and in part by funds from the Department of Mechanical Engineering at Penn State University.

Author information

Authors and Affiliations

  1. Department of Mechanical Engineering, The Pennsylvania State University, University Park, PA, USA

    Charles El Helou & Ryan L. Harne

  2. Materials and Manufacturing Directorate, Air Force Research Laboratory, Wright-Patterson AFB, OH, USA

    Benjamin Grossmann, Christopher E. Tabor & Philip R. Buskohl

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  1. Charles El Helou
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  3. Christopher E. Tabor
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  4. Philip R. Buskohl
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Contributions

C.E.H. and R.L.H. designed the research. C.E.H. and B.G. performed the research. C.E.H., B.G., C.E.T., P.R.B. and R.L.H. analysed the data. C.E.H., B.G., C.E.T., P.R.B. and R.L.H. wrote the paper.

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Correspondence to Ryan L. Harne.

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Nature thanks Soosang Chae and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Extended data figures and tables

Extended Data Fig. 1 Full adder digital states.

(a) Logic diagram of the full adder with its corresponding (b) truth table. (c) A schematic (left) and experimental image (right) of the material and conductive network for the full adder operation as determined from the design process. (d) A schematic (left) and experimental image (right) of the 8 possible configuration states with the binary inputs (A B C)2 shown in green and output (QCout QSum)2 in red. Connected networks for each output are bolded and highlighted in green or yellow.

Extended Data Fig. 2 Analysis of unit cell designs.

Three 1-bit unit cell designs with a Buffer gate conductive network are explored to tailor the mechanical uniaxial and shear force for the digital bit input. Schematics of the three unique designs are illustrated here: (a) Design I, (b) Design II and (c) Design III. The designs demonstrate independent bi-state self-contact and reconfigurable mechanical-electrical networks. The contact angle design parameter θcont and the centre shape geometry may be cultivated to design unit cells that require shear-dominated forces and low vertical displacements, such as Design III. The Boolean mathematical framework introduced in this research may be applied to various n-bit material systems that are sensitive to broad force environments.

Extended Data Fig. 3 2-bit adder digital states.

(a) Logic diagram of the 2-bit adder with its corresponding (b) truth table. (c) A schematic (left) and experimental image (right) of the material and conductive network for the 2-bit adder operation as determined from the design process. (d) A schematic (left) and experimental image (right) of the 16 possible configuration states with the binary inputs (A1 B1 A2 B2)2 shown in green and output (QCout QS2 QS1)2 in red. Connected networks for each output are bolded and highlighted in green or yellow.

Extended Data Fig. 4 2-bit subtractor digital states.

(a) Logic diagram of the 2-bit subtractor with its corresponding (b) truth table. (c) A schematic (left) and experimental image (right) of the material and conductive network for the 2-bit subtractor operation as determined from the design process. (d) A schematic (left) and experimental image (right) of the 16 possible configuration states with the binary inputs (A1 B1 A2 B2)2 shown in green and output (QBout QD2 QD1)2 in red. Connected networks for each output are bolded and highlighted in green or yellow.

Extended Data Fig. 5 2-bit multiplier digital states.

(a) Logic diagram of the 2-bit multiplier with its corresponding (b) truth table. (c) A schematic (left) and experimental image (right) of the material and conductive network for the 2-bit multiplier operation as determined from the design process. (d) A schematic (left) and experimental image (right) of the 16 possible configuration states with the binary inputs (A1 B1 A2 B2)2 shown in green and output (QP4 QP3 QP2 QP1)2 in red. Connected networks for each output are bolded and highlighted in green or yellow.

Extended Data Fig. 6 Analysis of n-bit adder scalability.

We utilize the automated design tool to design 1- to 6- bit adders to understand the material scalability with increasing n-bits in the adder operation. Two plots illustrating the relationship between the quantity of bits in an n-bit adder operation and the quantity of (a) switches and (b) material unit cells for the Standard Sum of Product (SSoP) and the Quine–McCluskey Sum of Product (QMSoP) design methods. The top plots illustrate a log10 scale and the bottom plots illustrate a linear scale for the quantity of switches and unit cells. The QMSoP reduces the material size by 31% in the 2-bit adder and by 92% in the 6-bit adder.

Extended Data Fig. 7 Comparison of material design methods.

Three methods are explored in this research that are capable of combinational logic network programming on soft material substrates. Schematics of the material and conductive network for the 2-bit adder by utilizing (a) the Standard Sum of Product (SSoP), (b) the Quine–McCluskey Sum of Product (QMSoP) and (c) the Substitution Method (SM). Compared to the SSoP, the QMSoP 2-bit adder significantly reduces both the quantity of switches and unit cells to 32 and 44, respectively. The SM further reduces the 2-bit adder to 24 switches and 36 unit cells.

Extended Data Fig. 8 Multilayer integrated circuit material.

A five-layer material system is utilized for the 86-gate combinational logic operation. (a) A schematic of a single layer 4-bit mechanical platform. (b) An experimental image illustrating the five-layer material system in the casing with respective dimensions. Five layers are chosen to distribute the 15 total digital outputs. A schematic (left) and experimental image (right) of the material and conductive network for layer (c) 1, (d) 2, (e) 3, (f) 4 and (g) 5 as determined from the design process. Each layer is only 12 conductive columns wide, which permits more straightforward digital actuation based on the urethane rubber material chosen here. In experiment, 16 column layers are utilized. The outer 2 columns are added without conductive traces on each extremity to improve self-contact at the boundary unit cells.

Extended Data Fig. 9 Embedded layers for computing-dense mechanical integrated circuit material.

(a) A schematic of a 2-bit adder with three stacked layers that contain the QS2, QCout, and QS1 on layers 1, 2 and 3, respectively. All layers are powered by the same Vcc terminal (cyan). (b) Experimental image showing the three layers made with cast urethane rubber substrates and Ag-TPU networks. (c) Image of commercial dual extrusion printer as it simultaneously prints the substrate and conductive network of a 2-bit adder by the layer-by-layer fabrication method. Photos of 2-bit adders as fabricated using the (d) casting and (e) additive manufacturing techniques. (f) Experimental results showing three digital input and output combinations for the cast (top) and additive manufactured (bottom) samples.

Supplementary information

Supplementary Information

This Supplementary Information file contains two sections with Supplementary Figs. 1–4 and additional references. Section 1: Substitution method of network topology formulation; Section 2: Design strategy tutorial: Quine–McCluskey sum of product (QMSoP).

Supplementary Video 1

This video demonstrates an 86-gate combinational logic operation illustrated in Fig. 4. This operation contains four digital inputs, A1, A2, B1 and B2. The 2-bit number B (B2B1)2 is simultaneously added and multiplied with the 2-bit number A (A2A1)2. The binary outputs are decoded to a two seven-segment number display with a, b, c, d, e, f and g independent segments. Furthermore, the magnitudes of the addition and the multiplication results are compared through a 4-bit magnitude comparator operation. Such operation results in three outputs, cm1 (<), cm2 (>) and cm3 (=). Thus, whenever a binary signal output is 1, the corresponding segment or comparator sign is illuminated. The display numbers corresponding to the sum and product are illuminated in red and blue, respectively. The numbers are mechanically input by hand through a combination of uniaxial compression and shear. The material casing ensures that all five layers uniformly collapse and exhibit the same collapse mode. The material is uncompressed partially, or fully between corresponding computations. Only 4 states are illustrated in the video, yet 16 functional configurations exist corresponding to the 16 possible arithmetic operations that may be performed and compared.

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El Helou, C., Grossmann, B., Tabor, C.E. et al. Mechanical integrated circuit materials. Nature 608, 699–703 (2022). https://doi.org/10.1038/s41586-022-05004-5

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