Abstract
Two-dimensional semiconductors are an attractive material for making thin-film transistors due to their scalability, transferability, atomic thickness and relatively high carrier mobility. There is, however, a gap in performance between single-device demonstrations, which typically use single-crystalline two-dimensional films, and devices that can be integrated on a large scale using industrial methods. Here we report the 200-mm-wafer-scale integration of polycrystalline molybdenum disulfide (MoS2) field-effect transistors. Our processes are compatible with industry, with processing performed in a commercial 200 mm fabrication facility with a yield of over 99.9%. We find that the metal–semiconductor junction in polycrystalline MoS2 is fundamentally different from its single-crystalline counterpart, and therefore, we redesign the process flow to nearly eliminate the Schottky barrier height at the metal–MoS2 contact. The resulting MoS2 field-effect transistors exhibit mobilities of 21 cm2 V−1 s−1, contact resistances of 3.8 kΩ µm and on-current densities of 120 µA µm−1, which are similar to those achieved with single-crystalline flakes.
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Data availability
Data that support the findings of this study are available from the corresponding authors upon reasonable request.
Code availability
The Python code (version 3.8.5) used in this study is available from the corresponding authors upon reasonable request.
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Acknowledgements
This work was supported by Samsung Advanced Institute of Technology, Samsung Electronics Co., Ltd.
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J. Kwon, M.S., K.-E.B. and J. Kim conceived the study. J. Kwon fabricated all the wafer-scale devices in this research and measured their electrical characteristics. M.S. produced the wafer-scale MoS2 films via MOCVD. J.Y. calculated the projected DOS of various types of MoS2–Au junction using DFT calculations. H.R. helped fabricate a single-crystal MoS2 FET by transferring a MoS2/hBN stack onto the bottom electrodes under the guidance of G.-H.L. D.-S.K. analysed the interfacial distances at different MoS2–Au junctions using scanning transmission electron microscopy. M.-H.L. provided a platform for the wafer-scale fabrication and electrical measurements of the MoS2 bottom-contact FETs. E.K.L. assisted with the low-temperature electrical measurements and analysis. M.S.Y. provided guidance for the experimental demonstrations of the bottom-contact FETs. H.-J.S. provided technical guidance and advice for proving this mechanism. J. Kwon, M.S., J. Kim and K.-E.B. wrote the paper. All authors contributed to the discussion.
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Extended data
Extended Data Fig. 1 Benchmarking FET performances of large area TMDs.
a. Benchmark data illustrating the Ion of MoS2 FET relative to the integration scale. MoS2 growth methods were categorized as thermal CVD (brown circle), Epitaxial growth on sapphire (navy square), and MOCVD (orange triangle). Here, CVD and epitaxial growth exhibit scaling limitations, as expected, but it appears that MoS2 grown via epitaxial growth shows better performance. Although MOCVD clearly has advantages in terms of scaling, it shows limitations in performance. But this work overcomes these limitations of MOCVD and demonstrates performance as high as chip-scale research. b. Benchmark data for the Ion and channel length of large-area MoS2 classified by patterning methods. Typically, photolithography is well-suited for large-scale integration; however, it leaves a significant amount of photoresist residue and involves relatively harsh wet processes, which can be detrimental to performance. On the other hand, e-beam lithography, whereas not well-suited for integration, utilizes a relatively clean e-beam resist (ER) and is suitable for fundamental studies through small-scale components, thanks to its high resolution. In this regard, the contact region, which is most influenced by photolithography, remains unexposed in the bottom contact geometry. Therefore, bottom contact devices exhibited performance equivalent or high to those fabricated using e-beam lithography and achieved a higher on-current compared to all other devices fabricated using photolithography. All data are based on Vds = 1 V, and some values are approximately extracted, so they may not be highly precise. In cases Ion at Vds = 1 V could not be obtained, values were unavoidably extracted at the specified Vds values in each paper, indicated within parentheses.
Extended Data Fig. 2 Grain size and uniformity of MOCVD-grown 200 mm MoS2 monolayer.
a. Photograph of a MOCVD-grown MoS2 film on a 200 mm SiO2/Si wafer. b. SEM images depicting changes as the growth cycle progresses. From these SEM images, it can be observed that the average grain size ranges from 50 nm to 100 nm. The relatively darker region in the rightmost image appears to be the bilayer patch, which is estimated to have approximately 20% coverage. c. Representative Raman spectrum of the MoS2 film. A peak and E peak respectively refer to the characteristic peaks of MoS2, the A1g and E12g peaks. Additionally, a peak from silicon substrate is also observed and indicated as Si, which plays a role as a reference. By analyzing the ratio of these peaks, the quality of the film can be indirectly checked. d. Raman spectrum map of the intensity ratio of the A1g peak to the Si peak, conducted on a 200 mm whole wafer. e. Raman spectrum map of the intensity ratio of the E12g peak to the Si peak, conducted on a 200 mm whole wafer.
Extended Data Fig. 3 TEM analysis of MOCVD-grown MoS2.
a. Dark-field TEM images of MOCVD-grown MoS2 obtained from varios angles. The image at the top center represents the corresponding diffraction pattern. b. Grain mapping image obtained by SADP (Selected area diffraction pattern) images. The grain size is estimated in range from 50 nm to 100 nm. c. HAADF-STEM (High-angle annular-dark-field scanning tunneling electron microscopy) images showing two grains with a grain boundary. d. Higher magnification and Gaussian-processed view of c. The red spheres represent Mo atoms, while the yellow spheres represent S atoms. It particularly demonstrates a S-deficient environment compared to Mo at the grain boundary.
Extended Data Fig. 4 XPS analysis of MoS2 samples with varying crystallinity.
a. XPS spectra of three MoS2 samples with different crystallinity. The top spectrum represents MoS2 single crystal, the middle one corresponds to polycrystalline MoS2 grown with a grain size of 500 nm, and the bottom spectrum is for polycrystalline MoS2 used in this study with a grain size of less than 100 nm. While the MoS2 single crystal exhibits minimal presence of Mo 6+ or 3+ peaks, the other two MoS2 samples show observable peaks for both Mo 6+ and 3+ states. Here, the intensity of the 6+ peak indicates the extent of oxidation to MoO3, while the size of the 3+ peak is directly related to the sulfur vacancy concentration. b. The Mo:S ratio and sulfur vacancy concentration extracted from the XPS spectra for each sample. Here, the Mo:S ratio has been normalized to the crystal sample. It clearly indicates that the polycrystalline sample indeed has a sulfur-deficient environment. Furthermore, the increase in sulfur vacancy concentration as the grain size decreases, coupled with a decrease in the Mo:S ratio, indirectly suggests that sulfur vacancies are generated at grain boundaries.
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Kwon, J., Seol, M., Yoo, J. et al. 200-mm-wafer-scale integration of polycrystalline molybdenum disulfide transistors. Nat Electron (2024). https://doi.org/10.1038/s41928-024-01158-4
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DOI: https://doi.org/10.1038/s41928-024-01158-4
